As electronic products such as mobile phones, notebooks and the like have been developed towards the direction of miniaturization, portability, ultra-thinness, multimedia and low cost meeting the public demands, a package mode with high density, high performance, high reliability and low cost and an assembly technology thereof have been developed rapidly. Compared with such expensive package modes as BGA (Ball Grid Array) and the like, novel packaging technologies which have been developed rapidly in recent years, for example, QFN (Quad Flat No-leadPackage) package has led to a novel revolution in the field of microelectronic package technology due to such advantages as good thermal and electrical performances, small size, low cost, high productivity and the like.
FIG. 1 is a structural schematic diagram of an existing QFN package structure. The QFN package structure includes a semiconductor chip 14, wherein bonding pads 2 are arranged on the semiconductor chip 1; pins 3 (lead frames), wherein the pins 3 are arranged around the surrounding of the semiconductor chip 1; metal conducting wires 4, wherein the metal conducting wires 4 are used for electrically connecting the bonding pads 2 on the semiconductor chip 1 with the pins 3 surrounding the semiconductor chip 1; a plastic package material 5, wherein the plastic package material 5 seals the semiconductor chip 1, the metal conducting wires 4 and the pins 3, the surfaces of the pins 3 are exposed on the bottom surface of the plastic package material, and the semiconductor chip 1 is electrically connected with an external circuit via the pins 3.
The existing package structure occupies a larger volume, which is unbeneficial to improving the integration level of the package structure.